1. Field of the Invention
The present invention relates to a semiconductor memory and a microprocessor, and more particularly, to an arrangement of an input buffer or the like suitable for realization of high-speed operation.
2. Description of the Related Art
As one example of a conventional semiconductor memory, there has been known such a conventional one as stated in ISSCC/86, SESSION XVI "STATIC RAMs THPM 16. 3; A 15 ns CMOS 64K RAM".
In the above-mentioned prior art, the semiconductor memory is constituted in such a manner that a plurality of memory cells are divided into a plurality of memory cell blocks (sometimes they are referred to as memory cell mats) and that input buffers for processing external signals which are accessed to these memory cell blocks are disposed along the side of the chip from its corner. Similarly, it may be supposed that in U.S. Pat. No. 4,616,310 or U.S. Pat. No. 4,831,433, the input buffers are located in the region of the side of the chip together with input pads.
Also, an input buffer of a memory such as a RAM or ROM of the conventional microprocessor is arranged to locate around the region where gate arrays including a memory array are formed (Japanese Patent Unexamined Publication Nos. 60-31239, 60-35532, and 62-285443).
On one hand, the semiconductor memory or the microprocessor is more and more required to shorten a period of operation time so as to process the signals at high speed. Therefore, it is important to minimize a memory access time during operation.
According to the prior art, however, since the input buffer is arranged to locate around the edge portion of the chip or the region of the memory array, a length of a wiring for transmitting the signals is sometimes elongated, when a relation in disposition between the input buffer and the memory cells to which the processed signals are transmitted is inappropriate. When the length of the signal pass is extended, a floating electrostatic capacity C and a resistance R of the wiring are increased. As a result, because a rising edge or a falling edge of a signal pulse to be transmitted is distorted so that the inclination of the pulse waveform becomes skew, the memory cell or a logic circuit which detects a signal at a certain threshold level operates after a delay in practice. An external signal including an already skew waveform scarcely causes the above-described delay.
However, waveforms of the external signals which have been processed through the input buffer are shaped so that the risings of the waveforms become steep. Succeedingly, the length of the wiring (amount of load) on the downstream of the input buffer has large influence over a signal transmission delay.
Moreover, as for the semiconductor memory in which input buffers are arrayed around one memory cell block, in the case where a signal has to be transmitted from the input buffers to a memory cell belonging to another memory cell block, there occurs a problem the same as the above that the length of the wiring on the downstream of the input buffer has large influence over a signal transmission delay.